New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog and UVM Environments

There is always a demand for learning something simply and quickly on your own in some corner of the world. The big challenge that I have faced with learning is how to find the right learning vehicle that helps me discover what I didn't already know in a short period of time. If you also struggle with this aspect, you should surely look at Cadence's Rapid Adoption Kits (or RAKs), available at http://support.cadence.com/raks.

Cadence RAKs help engineers learn foundational aspects of Cadence tools and design and verification methodologies using a do-It-yourself (DIY) approach. The app notes and tutorials provided with the RAKs also aid to develop a deep understanding of the subject.

Today, I introduce two new Verification IP RAKs that we launched in the last month. They demonstrate how you can improve your productivity and maximize the benefits of Cadence tools and technologies in the Verification IP space.

Integrating GMII VIP for SystemVerilog User

The first RAK provides a basic back-to-back GMII VIP example in pure SystemVerilog with an application note and four labs.

 It allows users to quickly get familiar with:

• Configuration (PureView, SOMA)
• Transaction generation
• Callback usage
• Error injection
• Debug using trace
• Quickly integrating VIP into the user's SV environment

 Generally, in a verification environment, a VIP can work as either a MAC or a PHY depending on the user's specific requirements.

This "Integrating GMII VIP for SystemVerilog User" RAK, using Cadence Ethernet VIP from the Verification IP Catalog of products, provides abundant features that address almost all the Ethernet verification aspects. In this RAK, an example is used where a PHY VIP mimicks the DUT.

The RAK and associated documents will help users who want to quickly integrate Ethernet GMII VIP into a SystemVerilog verification environment. 

Please download your copy now from http://support.cadence.com with your login credentials.

Integrating M-PCIe Verification IP

The M-PCIe standard defines a new logical layer mapping of PCI Express over the MIPI Alliance M-PHY specification. The M-PCIe will enable PCIe to operate over an established industry specification to enable aggressive power-management solutions while retaining all of the existing PCIe benefits.

The M-PCIe utilizes the upper layers of the PCIe, i.e., TL (Transaction Layer) and DLL (Data Link Layer), without any changes. The changes in M-PCIe with respect to PCIe are in the physical layer.

 Key features of M-PCIe include:

• Maintain compatibility with PCI Express programming models
• Multi-lane support, support lane configurations as defined in PCI Express Specification
• Support for PCI Express protocol as defined in PCI Express Specification
• Support for asymmetric link width configurations
• Support for dynamic bandwidth scalability
• Optimized for RFI/EMI
• Enable short channel circuit optimizations
• Support for all MIPI M-PHY high speed gears
• Support for M-PHY TYPE I MODULE only
• Support for MIPI M-PHY LS gear to be utilized for M-PHY parameter initialization
• Support of 8b/10b encoding for data encoding
• Support for shared and independent reference clocks

To help users create, configure, and instantiate the M-PCIe VIP in a UVM test bench, the Cadence Solutions team has developed this RAK on "Integrating M-PCIe Verification IP." The labs provided in this RAK give users a learn-by-doing experience in understanding the basic usage flow. This RAK is geared to users of the M-PCIe VIP from VIPCAT releases.

The purpose of this RAK is also tofamiliarize users with Cadence VIP terminology and concepts of SOMA. It will also provide details on how to Integrate VIP with DUT using an example—how to create a SV-UVM testcase for defining PCIe/M-PCIe transfers—along with providing debugging tips using the trace file.

Please download your copy now from http://support.cadence.com with your login credentials.

We are covering following technologies through our RAKs at this moment:

• Synthesis, Test, and Verification flow 
• Encounter Digital Implementation System and Signoff Flow
• Virtuoso Custom IC and Signoff Flow
• Silicon-Package-Board Design
• Verification IP
• SoC and IP-Level Functional Verification
• System-Level Verification and Validation with Palladium XP Platform
• Mixed-Signal Verification and Implementation Flows

Please keep visiting http://support.cadence.com/raks to download new RAKs as they become available.

Please note that you will need the Cadence customer credentials to log on to the Cadence Online Support http://support.cadence.com, your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies.

Happy Learning!

Sumeet Aggarwal