Just as IP components offload design effort, verification IP (VIP) components offload verification effort. VIP components are used to monitor traffic and substitute for selected master and slave components to enable controlled stimulus generation and coverage collection within an SoC design. To be effective in verifying CHI-based designs, the VIP must deliver three major capabilities. They are:
- Stimulus generation: Mimicking all possible scenarios to cover the full verification space
- Coherency checking: Ensuring coherency and system compliance with the CHI specification
- Coverage: Measuring functional coverage and ensuring verification completeness
1) Stimulus generation
The complexity of verifying CHI-based designs requires the use of verification IP that understands the protocol behavior of the various types of CHI masters, slaves, and coherent interconnects in the system. This offloads the user from having to know the intricate protocol details required to create legal (or illegal) transactions.
VIP that purports to mimic processor behavior must create stimulus that takes into account the protocol rules, includes a cache model and takes into consideration its state, and incorporates any design-specific constraints when generating transactions. The VIP must also calculate timing correctly according to the bus state.
2) Coherency checking
Each master and slave must be verified individually to ensure its compliance with the specification. While it is very important, it is not enough. The CHI VIP must be teamed with an interconnect VIP component – Interconnect Validator - that watches traffic on all the interconnect’s interfaces. This is necessary to ensure coherency of the full system. This means the CHI VIP and Interconnect Validator are required to perform two key tasks:
a) Ensure that each individual component (e.g. processors, memory) behaves correctly
b) Monitor the interconnect to ensure that communication between all components is accurate and in compliance with the CHI specification
Item (a) is enabled by the CHI VIP's master and slave agents. Once the user has integrated the SoC's IP blocks with the interconnect, the VIP can be used as a passive agent so it can monitor each individual bus interface to ensure protocol compliance.
To enable item (b), a separate Interconnect Validator is required. Without such an interconnect VIP, it is impossible to ensure full system coherency. This monitor must check data integrity and correctness of the interconnect itself to be sure it is behaving in compliance with the CHI specification.
3) Coverage
Simply defining all the complex scenarios to be tested is a major investment in and of itself. Yet, this is not sufficient. A CHI verification solution must also enable users to measure and ensure completeness of the verification space.
A functional coverage model is used as the metric for determining verification completeness. Therefore, it is imperative that the VIP provide the complete coverage map based on the CHI specification.
Beyond the protocol coverage there is also a need for system-level coverage which enables verification engineers to see which masters communicate with which slaves, which masters have been snooped, etc. Such a coverage model is an integral part of Interconnect Validator and will be discussed in-depth in the next installment of the CHI verification blog. Stay tuned!
Dimitry Pavlovsky