Consumer demand for entertainment and communication is changing the architecture of your electronic devices. And Cadence is providing key IPs necessary for SoC developers to quickly bring their products to market. Today Cadence is unveiling its first-silicon results for both DDR4 and LPDDR4 IP on TSMC's 16nm FinFET Plus (16FF+) process, with test chips operating at 3200Mbps. This speed can support the computation requirements for tomorrow’s high-resolution video and data bandwidth requirements of mobile, cloud, and networking devices. Figure 1 shows the fully integrated LPDDR4 package-on-package (POP) test chip and memory.
Figure 1: Cadence LPDDR4 POP test chip with SK Hynix LP4 3200 memories
TSMC shared some of the results from bringing up these systems at the TSMC Symposium, April 7, 2015, in San Jose, California. High-speed measurement results were made possible by state-of-the-art Tektronix scopes and new DDR/LPDDR analysis packages. The DDR/LPDDR controller and the PHY (driven by internally developed custom software) are integrated into the test chips. The LPDDR4 POP board included 3200 speed LPDDR4 memory from SK Hynix. The DDR4 DIMM board supports single- or dual-DIMM configurations with unbuffered DDR4 DIMM from Micron.
This blog highlights the details of the silicon test chips, testing environments, and validation of both IPs operating at 3200Mbps.
High-Speed Memory System Platform
Two hardware test platforms were developed, one for DDR4 and another for LPDDR4. To further enable development for mobile products, the LPDDR4 was implemented using advanced POP packaging technologies and quad-channel LPDDR4 3200 POP memory from SK Hynix. The LPDDR4 controller and PHY test chip was fabricated in TSMC's 16FF+ process. The test board shown in Figure 2 includes a number of advanced hardware and components. Testing was done with LPDDR4 POP memory from SK Hynix clocked at 3200Mbps.
Figure 2: LPDDR4 POP board with 3200Mbps SK Hynix memories
For DDR4 DIMM memory testing, the DIMM test board with two slots can support single- or dual-DIMM configuration. To allow higher performance evaluation, a single unbuffered 2400 DIMM from Micron is placed at the far end slot and overclocked at 3200. The DDR4 controller and PHY test chip was fabricated in TSMC's 16FF+ process. Testing was done at 3200Mbps.
Figure 3: DDR4 memory board with Micron memories
Silicon Results
The LPDDR4 PHY IP solution uses an advanced clocking architecture, resulting in a low jitter data eye as shown in Figure 4. The figure illustrates a very clear data eye with DQS precisely centered on the data eye with traffic running at 3200Mbps.
Figure 4: LPDDR4 traffic at 3200Mbps
The DDR4 PHY IP solution uses the same advanced clocking architecture used in the LPDDR4 solution, resulting in a low jitter data eye as seen in Figure 5. The test chip passes with random traffic patterns at 3200Mbps.
Figure 5: DDR4 traffic at 3200Mbps
Industry Partners
The key to successful delivery of DDR PHY IP for customers is careful design across the SoC, package, board, and system challenges. Part of that involves collaboration with industry leaders such as Nexus, SK Hynix, Tektronix, and TSMC in finding solutions to the technical challenges.
In 2015, our engineers collaborated with Nexus and Tektronix on a DesignCon paper for DDR3 interposer design and testing. The joint effort helped advance further understanding of the design, modeling, and measurement challenges, which paved the way to LPDDR4. This was documented in the paper “Designing High-Performance Interposers” at DesignCon 2015. The paper provides insight into the design, validation, and simulation of high-performance interposers. The teams also gained recognition at DesignCon as the paper was selected as one of the finalists for best paper award under the System Co-Design Chip/Package/Board Modeling & Simulation category.
The partnership with Tektronix enabled us to develop solutions for both design and testing that customers will have available when they are ready to bring their design to market. Figure 6 shows the Tektronix equipment used to perform the testing. Learn more about their solution.
"There’s no question that LPDDR4 makes validation far more complex and challenging for the entire mobile memory ecosystem, from silicon vendors to system integrators," said Brian Reich, general manager, Performance Oscilloscopes, Tektronix. “Through our partnership with Cadence, together we can bring this exciting technology to market, from high-performance Tektronix oscilloscopes, analysis and probes to Cadence IP and modeling/simulation tools."
Figure 6: Tektronix DDR testing equipment
Next-generation SoCs and mobile memories continue to shrink in scale to meet the performance and form factor requirements in portable and IoT devices. The physical dimension of 0.4mm BGA pitch LPDDR4 POP makes traditional probing methods with oscilloscope probes inaccessible. For post-silicon validation measurement, Cadence is using both in-house and marketplace solutions from Nexus Technology to measure the signals between the DDY PHY controller and the memory. Figure 7 shows some of our LPDDR4 testing using the LPDDR4 interposer design from Nexus Technology.
Figure 7: LPDDR4 POP Testing with Nexus LP4 Interposer and Tektronix test probes
Cadence’ Sigrity solution was used for system co-design simulations to check the signal integrity of the interface and potential impact of the interposer and probe loading to the interconnects. Learn more about this project.
Summary
Cadence has been developing high-performance DDR IP since acquiring Denali five years ago. In this short time, we have maintained leadership by being first offering DDR4 IP in 2012, and by delivering one of the first DDR4 manufactured on the 16FF process. Several customers are using our DDR4 IP, including HiSilicon. And we are working with several lead customers integrating the LPDDR4 PHY and controller into their next low power SoC. Our customers leverage our experts in DDR for system architecture and selecting the right DDR technology. And we continue to innovate solutions for systems that require high-performance DDR/LPDDR memory IP.
Steven Brown
Other Resources
- More information about Cadence DDR/LPDDR PHY IP
- More information about Cadence DDR/LPDDR Controller IP
- New LPDDR4 Standard Features
- Cadence LPDDR4 Comprehensive Signal Integrity Solution
- Multi-protocol DDR IP, DDR and LPDDR IP controller and PHY solutions
- Verification IP memory models for DDR and LPDDR
- How Verification IP Can Minimize LPDDR4 PHY IP Verification Complexity
- External Memory Architectural Choices for Terabit Class Devices, by Dinesh Venkatachalam, Broadcom