Think that DAC is all about EDA tools? Not anymore. This year there are over 100 presentations in the IP track, plus other sessions that are all about IP. After all, it’s almost impossible to find a chip design these days that doesn’t employ some type of IP.
Come see many of us from the IP Group at Cadence at DAC, June 7 – 11, at Moscone Center in San Francisco. You can’t miss the Cadence booth—we’re in the far right back corner, booth 3515. An IP representative will be there, and we’re even featuring IP experts in our Expert Bar:
- Monday 12noon – 2 pm: IoT Design with Efficient DSPs—Chris Rowen and Paula Jones
- Tuesday 10am – 12noon: Picking the Right Memory IP—Lou Ternullo and Jeffrey Chung
- Tuesday 2pm – 4pm: Simplify SoC Verification with VIP—Tom Hackett, Sameek Chanda, and Remi Clavel
- Tuesday 6pm – 7pm: SoC Design with Efficient DSPs—Neil Robinson and Chris Rowen
- Wednesday 12noon – 2pm: Picking the Right Memory IP—Lou Ternullo and Jeffrey Chung
- Wednesday 4pm – 6pm: Simplify SoC Verification with VIP—Tom Hackett, Sameek Chanda, and Remi Clavel
We’re also hosting in-depth technical sessions in our booth—sign up here:
- Osman Javed: Bringing PCIe Performance to Mobile Platforms, Monday 10:00am
- Amir Bar-Niv: Addressing IP Challenges in Advanced-Node SoCs, Monday 12noon
- Tom Hackett: Indago Protocol Debug App Cuts SoC Verification Time, Tuesday 1:00pm
- Avi Behar: SoC Performance Analysis with Interconnect Workbench, Monday 3:00pm
- Chris Rowen: Always Alert: New Processors for Low-Energy Wireless Sensor Nodes, Tuesday 4:00pm
- Chris Rowen: Designing and Selecting Instruction Sets for Vision, Wednesday 5:00pm
We’re doing so much more than this! Be sure to stop by and see:
- Chris Rowen: Sunday 8:30am-5:00pm, room 304—Design Automation for HPC, Clouds, and Server-Class SoCs
- Tom Wong: Monday 5:30-6, room 101—Integration Challenges of Third-Party IP
- Chris Rowen: Monday 4:30-5:30, Room 101—Design in the Eye of the Hurricane: Building Optimal Vision Processing Subsystems
- Martin Lund: Tuesday 2:30-3, room 101—IP Management in 2020 (panel)
- Osman Javed and Shrinivasan Jaganathan: Tuesday 4:30pm-6pm, Poster session on exhibit floor—Utilizing PCIe Performance for Mobile Platforms
- Anurag Jain: Tuesday 4:30pm-6pm, Poster session on exhibit floor—DDR4 Subsystem Implementation on 16FF+
- Philip Pun: Tuesday 4:30pm-6pm, Poster session on exhibit floor—Simulation and Modeling of DDR4 Memory Interface and Interposer test Fixtures
- Chung Huang: Tuesday 4:30pm-6pm, Poster session on exhibit floor—DDR IP Power and Noise Optimization Techniques for High-Speed Memory Subsystems
- Chris Rowen: Thursday 4-5:30pm, Panel—"The Long and Winding Road to IoT Connectivity: Are We There Yet?"
DAC exhibit hours are Monday and Tuesday, 10am – 7pm, and Wednesday, 10am – 6pm. See you there!
Paula Jones