As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible. There is nothing quite so sad as a shiny new gadget that falls short because of poor memory performance (something easily avoided with the right IP), or trying to install a new app only to have to decide what you must delete to make room for it.

It’s been a busy few weeks for the IP team with the announcement of support for two new memory technologies – DDR4 and Wide I/O.

With Wide I/O and DDR4 offering significantly improvements for the device classes they target for, it’s exciting to contemplate how design teams will leverage them to deliver on the next wave of devices. So whether it’s a high performance gaming desktop, a sleek new tablet, or enterprise equipment that interests you, new memory technologies will play a key role.

Learn more about Cadence Design IP for Memory and Storage.

Neil Hand

Related Blog Posts

Wide I/O Memory and 3D ICs -- A New Dimension for Mobile Devices

Memory and Storage Control -- Next Frontier for Third-Party IP?

The answer is "yes, you must initialize it" but the reason may be surprising to many people: DRAM contents are not lost when the power is turned off! I stumbled upon this great research paper from Princeton University this week which is interesting in itself (it talks about how most encryption is vulnerable to hacking through the DRAM), but also has some interesting data about just how long data can persist in DRAM. The researchers found that some of the bits in DRAM were still capable of holding charge minutes after losing power, even when the memory is removed from the machine entirely. A video clip located here shows the process they used, and at one point shows them removing a DIMM from one machine and putting it into another - and then retrieving all the data out of that DIMM!

For those interested in information technology security, this data suggests the importance of encrypting the contents of DRAM as well as the contents of a hard drive - but that was not the concern of the customer who asked the original question.  When using ECC (Error Correcting Codes) in DRAM, a typical arrangement is to have 64 bits of data and 8 extra ECC bits that hold a SECDED code that is capable of correcting a one-bit error and detecting a 2-bit error in the 64 bits of data (Cadence's DRAM controller allows other sizes like 32&7, 32&4, 16&2 but let's stick with 64&8 for now).

The problem arises when the system needs to write less than the full 64 bits of data, and the memory controller needs to do a Read-Modify-Write (RMW) operation on the memory location to be able to preserve the part of the write data that was previously in that memory location that is not being overwritten by the current write operation.  If the 64 bits of data that are being partially overwritten have stale and partially-degraded memory contents from the previous time the DRAM was used (for example, if the machine was turned off momentarily and then turned back on again) then when the memory controller tries to read that memory location it will encounter ECC errors when it tries to do the read portion of the RMW operation.

Wait a minute, don't newer DRAMs like DDR3, DDR4 and LPDDR2 have a reset pin?

Yes they do - but that reset only resets the memory state machines; it is not guaranteed to reset (or not reset) the memory contents.  

Umm... okay, so what do I do about it?

I'm glad you asked! The simplest thing is never to do masked or partial word writes - then any time you might use a memory location that had old data in it, you will overwrite it completely. You system will still have lots of errors, though, if you happen to read a location in memory that has not been written to yet. This solution is impractical for systems working with short and irregular data packets like networking and video.  

In simulation, you can use advanced properties of your Verification IP (VIP) such as Cadence's VIP Catalog Memory Models (formerly known as Denali MMAV) to set a pre-assigned value into all the DRAM when you start simulations, so that you don't have to initialize the DRAM in simulation every time.  Just be sure to do your final signoff on a memory with randomly assigned background data and do take care to initialize it.  

For your real system, you can write a program for your CPU that writes to every DRAM location, although this could take a while. Cadence's DRAM Memory Controller IP has a BIST option that will run a hardware test on the DRAM as well as leave the DRAM's ECC check bits in a correctly calculated state and which will run significantly faster than in software.  

Now... how do I encrypt that DRAM?

Maybe a topic for another blog...  

Marc Greenberg

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in the ASIC reference card was attached to a LeCroy Summit T3-16 analyzer and Summit Z3-16 exerciser platform to demonstrate the Cadence PCI Express 3.0 core with traffic running at 8 GT/s per lane.

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification.The PCI Express Gen3 IP successfully implemented in silicon advanced capabilities like Single-Root I/O Virtualization (SR-IOV), as well as the latest engineering change notices (ECNs) including ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.

To learn more about the Cadence Design IP for PCI Express Gen3 IP, please come back next week to see the PCI Express Gen3 IP video of the demonstration.

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser.  In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:

• The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification
• The demo shows Cadence's PCIe Gen3 high performance x8 configuration operating at full speed 500Mhz clock rate with a transfer rate close to 8GT/s
• The display trace shows the PCIe Gen3 IP transition from Gen1 speed 2.5 GT/s to Gen3 8GT/s
• LTSSM flow graph showing equilibrium between upstream and downstream packet transfers and speed of operation at 8GT/s

Please come back soon to view Part 2 of 2 showing the advanced features of Cadence's PCI Express Gen3 IP.

Stella Murphy

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.

Why is it important? The two main advantages of an SR-IOV PCIe device are:

• It allows multiple OS’s to have their own private view of the PCIe device
• It helps improve I/O performance by reducing  latency of the hypervisor

Please see the video below for more details. Also, please comment on how you've seen PCIe Gen3 SR-IOV used in different applications.

Stella Murphy

As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve.

Martin Lund, Senior Vice President at Cadence, was recently interviewed at DAC2012 by EE Times’ Brian Fuller. Martin laid out a vision for commercial IP, describing requirements for integration, test benches, certification environments, integrity models, and test chips to deliver high quality, reliable IP that will truly reduce costs and improve time to volume.

Check out the interview here: http://video.eetimes.com/playlist-video/dac-2012/1653470487001/eetimes-live-stream-dac-2012-martin-lund/1675544149001 

Neil Hand

It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly in silicon in a real system.

We thought we would raise some eyebrows since, as of today, there are very few products in the market that utilize the full power of the PCIe Gen3 protocol, let alone those that have been designed using a commercial IP offering. Cadence has been working very closely with its early PCIe Gen3 customer, PMC-Sierra, to develop a Gen3 X8 Dual-mode controller IP with full support for the PCIe 3.0 specification, including SR-IOV and all ECNs. This IP interfaces to the PCIe bus on PMC's 6Gb/s SAS/SATA controller chip that is installed in Adaptec's RAID controller card.

In this demo we are showing the high storage data throughput between the Intel Sandy Bridge PC and the array of SATA SSD drives via the Adaptec HBA card. All the hardware used in the demo, with the exception of the soon-to-be-available Adaptec card, uses off-the-shelf components that you can buy from any hardware store. The demo is around 4 minutes in length, and I invite you to take a look. And if you are a PCIe geek as I am, this might take your breath away!

Click on the icon below to view the demo, or click here.

Ashwin Matta

Let me start this entry on a bit of a personal note. As a Pole, I was very happy to learn some time ago that the 2013 European meeting of the MIPI Alliance would take place in my home country. Later, it turned out that Cadence was to acquire the IP business of Evatronix, the company I worked at. These events ended up taking place one right after another—on Thursday, June 13, Cadence completed its acquisition of the Evatronix IP business, and the following Monday, the MIPI Alliance meeting started in Sheraton, Warsaw—isn’t that a nice coincidence? That’s why I’m very happy to report from this event, which is also my first Cadence blog entry.

MIPI Alliance is a non-profit organization that focuses solely on low-power interfaces developed with the mobile market in mind. Since it was set up in 2003, it has already developed over 30 different specifications, and most of them are now standard in the application processors that we carry with us in our smartphones.

Personally, I am amazed how smart MIPI is. Instead of focusing on technology, they focused on the vertical market and now they have a standard for pretty much every connection there is within a mobile device. This includes DSI (Display Serial Interface), CSI (Camera Serial Interface), and BIF (Battery Interface), and the list goes on. Look at the diagram below—is there anything that you’re missing?

The current portfolio of MIPI interfaces. Source: MIPI Alliance.

I think the reason that MIPI is so strong, and able to meet mobile market demands "on the spot," is that they are extremely productive during their meetings, and they have market-leading companies driving the development. Rick Wietfeldt, the head of the Technical Steering Group within MIPI, is from Qualcomm, so what company would be better positioned for technical development if not the market leader for mobile application processors itself?

"MIPI continues to develop optimized interfaces to meet the key mobile terminal careabouts of performance, cost, and power consumption, while minimizing EMI from both fast- and slow-speed interfaces," said Rick in his presentation. "MIPI also continues expansion and exploration with industry organizations to seed its technology into new mobile and mobile-influenced opportunities."

Another big factor behind MIPI’s power is their never-ending, aggressive development. Some will say that at MIPI, there are currently so many acronyms that you can easily get lost, and new ones are coming at a very fast rate, but that it is because MIPI aims far beyond what we currently need for mobile device development. For the majority of companies that are MIPI adopters, this means the specs they have access to have already been tested, and when ratified, they are very safe to use.

Last, but not least, are the partnerships. MIPI was smart enough to engage with both USB-IF and PCI-SIG to develop some standards together—SuperSpeed InterChip (SSIC) and Mobile PCI Express (M-PCIe), respectively—and now have powerful allies instead of potential enemies. Amazing.

During the MIPI Alliance meeting, there were numerous sessions focused on different specifications that are in development now. Depending on membership status, companies were allowed to take part in various sessions. The plenary session outlined the direction MIPI is heading in the future, as well as provided feedback from marketing and technical working groups.

A nice touch at all MIPI meetings is Demo Day. Cadence was represented at three tables thanks to acquisitions of both Cosmic Circuits and Evatronix, both of which applied for a table before the deals were closed. It was a good opportunity to network a bit among fellow MIPI partners.

The conclusion I drew from the meeting is that MIPI is stronger than ever because the mobile market is stronger than ever, and it won’t change in the near future—MIPI is here to stay. I cannot recommend strongly enough for any company that could benefit from MIPI membership to join immediately—it will be definitely money well spent.

Jacek Duda

We just finished the PCI-SIG 2013 conference at the Santa Clara Convention Center, and our M-PCIe demo was a big hit.  We actually demoed it for the first time the week of June 17, 2013, at the MIPI Alliance’s European Meeting in Warsaw.

Visitors throng to Cadence's M-PCIe Demo at PCI SIG, Santa Clara, 2013. Martin James of Cadence answers questions.

It was fitting that Cadence would be the first to demonstrate the PHY and controller IP with high-speed links across M-PHYs. Cadence was one of the initial sponsors of this ECN. The Cadence design team actively participated in the discussions and contributed to the specification. Our design is a native RMMI based implementation, unlike implementations that convert PCIe to M-PCIe using a shim layer. The shortcut via the shim might be tempting, but does not help realize the power advantages of the protocol!

The Cadence booth also had presence from our Sigrity product line and Verification IP team, representing the broad presence in this arena. Guoqing Zhang of Cadence also presented a talk on testing and verification of NVMe PCIe Devices. 

 

The Cadence booth at PCI SIG Developers Conference 2013: Center Stage 

If you’re reading this, you must have heard about the M-PCIe specification that has just been announced by two very important standardization bodies in the semiconductor industry—MIPI Alliance and PCI-SIG. According to the press release that was released during the PCI-SIG event last month, “M-PCIe specification provides uncompromised scalable performance while delivering a consistent user experience across multiple mobile platforms.” This sounds very appealing, but exactly does it mean to the mobile SoC developers?

As I wrote in my previous post, the MIPI Alliance is known for the introduction of over 30 specifications targeted for mobile platforms, and has managed to do this in just 10 years. Certainly, 10 years is a lot of time, and mobile market is the fastest growing segment of the semiconductor industry, but still the number is impressive. Even more impressive is the fact that these specs have been adopted by the major players in the market, and thus have made their way into pretty much every mobile device there is.

PCI-SIG, on the other hand, is very conservative when it comes to giving birth to a new child. Actually, they have been active for twice as long as MIPI and developed 10 times fewer specifications than their latest partner. But don’t let this unfavorable comparison fool you. The money in the PCI business is still far more than in the all MIPI Alliance specifications combined, mostly thanks to the wide adoption of the PCI, and later PCI Express bus in the infrastructure, storage, and PC markets.

This clash of the titans of their domains sends a very important message to the whole semiconductor market. It shows how much convergence there is between mobile and infrastructure, and the direction is now to take advantage of this fact. Actually, key players in both markets have been observing each other for quite some time, and actions have already been taken. ARM and Intel are perfect examples here, with ARM’s A57 targeted also for server architecture and Intel’s Atom processors implemented in mobile devices. While there is little chance of these two joining forces, there also are no obstacles for the standardization bodies coming from different worlds to create a synergy effect.

World premiere of the first native M-PCIe controller by Cadence at the MIPI Alliance event on 18 June.

For design IP providers, M-PCIe is a perfect opportunity to deliver to market a solution that has the best of both worlds, and to become ambassadors for the new technology. It’s no secret Intel is the founding father of the PCI architecture, and Qualcomm keeps the MIPI Alliance going strong.

Design IP leaders like Cadence and Synopsys already have solutions on M-PCIe. Cadence showed their demo on 18 June, at the MIPI Alliance Demo Day in Warsaw, Poland, while Synopsys demonstrated the IP a week later, at the PCI-SIG conference. This sequence actually makes Cadence the first company to reveal a working M-PCIe solution, and contrasts with the statement made by other IP providers recently. Also, I’ve just learned that only the Cadence solution is a native M-PCIe controller that runs without any “regular” PCI conversion layers in between.

Martin James of Cadence at the PCI-SIG Developers Conference, where M-PCIe was announced.

Altogether, the engagement from the standardization bodies, major chip manufacturing companies, and design IP leaders makes the M-PCIe the standard to watch. For SoC companies, M-PCIe is definitely something that they want to give a thought to before they leave for well-deserved holidays. Definitely better before than after.

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers, devices and transaction types. Cadence VIPs also support integration and traffic generation in all popular verification environments.

During the past year, I have seen engineers struggling with debug for VIP based simulations. The questions that bother them most are:

• How can I generate tests quickly and efficiently to ensure that the design is compatible with standard Interface requirements?
• How are extensive protocol checks and coverage built into Cadence VIP, ensuring the high quality of VIP design under test?
• How can I make the best use of trace files in debugging VIP design simulations?
• How can I create, configure and instantiate VIPs in the testbench?

In this blog, I will talk about how Cadence staff and engineers are developing some app notes to help users debug using trace files. I will give you references to complete documents for following VIP - AHB, USB2.0, PCIE2.0, USB3.0, SSIC and LFPS Signaling in USB3.0. 

1.       AHB is a new generation of the AMBA bus that addresses the requirements of high-performance synthesizable designs. AMBA AHB is a new level of bus which sits above APB and implements features required for high performance, high clock frequency systems including burst transfers, split transactions, single cycle bus master handover, and wider data bus configurations. AMBA AHB supports a Lite version and a Regular version. AMBA AHB Lite addresses the requirements of high performance synthesizable designs. It supports a single bus master and multiple slaves. AMBA AHB Regular version supports multiple masters, multiple slaves and an arbiter to handle the arbitration between masters.

Sharath Siddappa, Lead Application Engineer at Cadence, prepared an Application Note titled Debugging AHB VIP using trace file that gives tips on how to debug AHB simulations with Cadence AHB VIP (based on Purespec^TM API) from the Denali trace file. It also shows how to debug specific scenarios like reset, transactions, or callbacks.

This document will help users debug Cadence AHB VIP using trace files. It provides egrep/perl commands to extract information about various AHB transactions that would help debug failures better. The commands can be used as is by just changing the instance IDs (in bold and red) according to user's requirements. Also, the document captures commands for basic debugging. Users can combine the commands or write new commands to meet debug requirements.

2.      In an Application Note titled Debugging the Trace File for USB 2.0 Verification IP, Rishubh Garg, Member of Consulting Staff at Cadence, gives you some tips on how to debug USB 2.0 simulations with Cadence USB 2.0 VIP from the Denali trace file. It shows how to debug specific scenarios like reset, suspend, resume, and packet flow.

3.      Responding to the increased demand for VIP technical support and debugging documents at http://support.cadence.com, Nikhil Sharma, Sr. Solution Engineer at Cadence, stepped up to interact with users through his knowledge-sharing documents on debugging USB3.0, SSIC and LFPS Signaling in USB3.0 with the help of trace files.

If you have ever wondered how to create, configure, and instantiate PureSpec USB 3.0 VIP in the testbench, please see Nikhil's Application Note Integrating USB 3.0 VIP and Debugging Steps Using the Trace File, and note the tips for debug using the trace file generated during simulation

4.       SuperSpeed USB Inter-Chip (SSIC) defines a chip-to-chip USB based interconnect for mobile devices as well as other platforms. SSIC offers MIPI Alliance's M-PHY^TM high bandwidth and low power capabilities combined with SuperSpeed USB performance enhancements. The M-PHYSM interface, a high speed serial interface, targets up to 1.2 Gbps per lane with scalability up to 5.8 Gbps per lane and offers a low pin count and exceptional power efficiency. SuperSpeed USB offers a 5.8 Gbps signaling rate per lane, up to 10 times faster than Hi-Speed USB (USB 2.0), enhanced protocol and power management and software model. Demand for higher speeds is strong in mobile consumer applications including video streaming, and SSIC fits well there.

This is another marvelous Application Note,Integrating SSIC VIP and Debugging Steps Using the Trace File, whereNikhil Sharma helps you create, configure, and instantiate PureSpec SSIC VIP in the testbench, and also provides you with tips for debug using the trace file generated during simulation.

5.       LFPS (Low Frequency Periodic Signaling) in Super Speed USB is used for sideband communication between the two ports over a link. It is done when normal SS packet transmission is not possible, and "out of band" messaging is required. The Cadence Purespec USB 3.0 VIP completely supports LFPS signaling as per USB 3.0 Specifications, for various stages with timing values as defined by specifications. In Cadence VIP, these timing values are configured through propriety SOMA timing attributes through Pureview.

However, Cadence USB 3.0 VIP provides full flexibility to change these values per user requirements (for example, cutting down simulation time) along with DUT timing parameters. Most challenges faced by users around LFPS Signaling occur during link training and initialization, which are mandatory for link up. Nikhil's paper Debugging LFPS Signaling in USB 3.0 VIP using Trace File addresses a very common setup problem faced by users.

6.       Last but not least, Mukul Dawar,  Sr. Solutions Engineer at Cadence, compiles his knowledge in this latest AppNote, Integrating PCIE 2.0 VIP and Debugging Steps Using the Trace File.  This AppNote helps users of the PureSpec PCIE 2.0 VIP from the Cadence VIPCAT 11.3 release create, configure and instantiate PureSpec PCIE 2.0 VIP in the testbench while debugging with the trace file generated during simulation.

To access the Application Notes, please login with your Cadence credentials at http://support.cadence.com

The Cadence Online Support - http://support.cadence.com is your 24/7 partner for getting help in resolving issues related to Cadence software or learning Cadence tools and technologies. If you are signed up for e-mail notifications, you are likely to get notices for new solutions, Application Notes (Technical Papers), videos, manuals, and more. 

In future posts I will talk more about Denali Migration Guide, NVMe Purespec VIP Usage, Verification Flow for USB, and Instantiating VIP models with SystemVerilog.

Happy Learning!

Sumeet Aggarwal

After talking about some tips for using trace files in debugging Verification IP simulations in my last blog post, here I am back again, as promised. This time I'll discuss and provide references for the Denali Migration Guide, NVMe PureView VIP Usage, Verification Flow for USB, Instantiating VIP Models with SystemVerilog, and finally Integrating USB 3.0 PHY DUT with PureView USB 3.0 VIP.

1. Many users have reported that they face issues in transitioning from the Denali Software Memory Models (MMAV) and PureSpec (bus VIP - now PureView) to the Denali versions of the same Verification IP within the Cadence Memory Model Portfolio and VIP Catalog.

To resolve those issues, Cadence VIP R&D and engineers (Josue Reyes, Ryan Badger and Amy Witherow) immediately provided a simple and effective migration guide, Denali VIP Migration Guide which is intended to help users migrate from Denali VIP software/licenses to the Cadence VIPCAT software release. It should be very handy in that migration.

2. The growth in usage of the PCI Express interface, and its different implementations offering different subsets of features, generated a need for a protocol standard that defines standard drivers and interoperability between implementations to shorten qualification cycles.

The NVM Express standard was designed to enable faster adoption and interoperability of the PCI Express interface. Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It defines a register-level interface that allows communication with non-volatile memory.

Mukul Dawar, Sr. Solution Engineer at Cadence, wrote the NVMe PureView VIP Usage Application Note. This document illustrates the steps that are needed to set up the NVMe (on top of PCIe PureView VIP) PureView model with the DUT, including how to set up memory areas (LBAs and PRP List). Examples (code snippets) are provided to explain how a user can create/send different admin and IO NVMe commands.

This document covers the integration and use of NVMe PureView VIP when performing verification of RC-Host and/or EP-Controller DUTs.

3. Nikhil Sharma, Sr. Solution Engineer at Cadence, provides help for all users of the PureSpec USB2.0, USB 3.0 and SSIC VIP from the Cadence VIPCAT 11.3 release in his latest Application Note titled Verification Flow for USB VIP. Here he helps define next level of integration for first time USB VIP users, and shows how to make sure that the right steps have been followed before VIP is ready to send USB transfers from test cases.

4. The Verification IP group at Cadence is also introducing a new form of instantiation to enhance the usability of VIP models in SystemVerilog -- a new kind of HDL instantiation interface that allows the user to connect to a VIP model using a SystemVerilog interface as a port. Kathy McKinley, VIP R&D, wrote the Application Note Instantiating VIP Models with SystemVerilog to explain this new functionality.

SystemVerilog users who want to connect to a VIP model using SystemVerilog port interfaces can take advantage of the new functionality rather than using a portmap to our model with their own SystemVerilog interface. Having the VIP nets bundled to share and pass to the user environment is a valuable enhancement. Users will also enjoy direct access using the SystemVerilog language.

This feature is available in a new Verilog/SystemVerilog integration library that is based on the IEEE 1800 VPI (Verilog Programming Interface). This means that instead of loading libdenver.so or mtipli.so files for simulation, the user will load the new library, libcdnsv.so. The VIP scripts provided with the release and irun provide options for choosing the new library.

The new functionality is for static module instantiation. UVM dynamic instantiation will be supported later. 

5. Setting up a verification environment for a USB 3.0 PHY design core can be one of the most challenging aspects of verifying a SuperSpeed Design. The PureView USB 3.0 VIP not only provides a simple way to set up the testbench for verifying a USB 3.0 PHY DUT, but also maintains a powerful capability to verify the PHY DUT "in and out."

Nikhil Sharma's newApplication Note Integrating USB 3.0 PHY DUT with PureView USB 3.0 VIP highlights important facts that are required to set up the testbench for possible configurations of PureView USB 3.0 VIP to verify a USB 3.0 PHY design core. This AppNote is geared to users of the PureView USB 3.0 VIP from the Cadence VIPCAT 11.3 release, and it will help users in integrating USB 3.0 PHY DUT with USB 3.0 VIP in all possible configurations.

Please login with your Cadence credentials at http://support.cadence.com to access the troubleshooting documents, Application Notes, videos and Rapid Adoption Kits from Cadence Online Support -- the Cadence Self-Help and Learning Portal for its customers. 

In my next blog, I will be introducing you to VIP Rapid Adoption Kits (RAKs) and illustrate a self-paced and complete workshop on Integrating USB3.0 and PCIE2.0.

Happy Learning!

Sumeet Aggarwal

The future of television is being defined by two key technologies: organic light-emitting diode (OLED) screens and ultra high definition (Ultra HD or "4K TV") standards. OLED is a display technology that makes colors pop like nothing you've seen before. 4K TVs deliver incredible sharpness and detail by packing in four times as many pixels as there are on the 1080p HDTVs in our living rooms.

Today HDMI 1.4b, the ubiquitous digital display standard, pipes content from a source (DVD player, Apple TV, Xbox, cable box, etc.) to your TV and it does a marvelous job in making your 1080p picture look good. HDMI 1.4b can also transmit a 4K video stream, but at a reduced rate of 24 to 30 frames per second (compared to 60 fps for broadcast 1080p content). The restricted bandwidth doesn't produce the smooth motion experience that consumers now expect.

Here is where HDMI 2.0 comes in. This next evolution of the HDMI specification is expected to support 4K resolutions at 60fps. Perhaps just as importantly, it will also support increased color rendition with 10 or 12 color bits vs. only 8 bits for 4K via HDMI 1.4b. While an increase from 8-bit color to 10- or 12-bit color doesn't seem like a big deal, it is. It will be an increase of billions of colors that the untrained eye can easily see and appreciate. Do you remember what made you switch from a color TV to HDTV - the impact of lifelike images?  Get ready for a déjà vu experience when you see the results enabled by HDMI 2.0!

While there will be great consumer benefits enabled by this new standard, there will also be great challenges for SoC developers.  The preceding HDMI specification updates were controlled by a small group of founders - Hitachi, Panasonic, Philips, Silicon Image, Sony, Thomson, RCA, and Toshiba. Now, HDMI 2.0 is being developed with input from the whole industry. In addition to the original founders, contributing companies include Apple, AMD, Intel, Microsoft, Cadence, Broadcom, ST Microelectronics, Samsung, Texas Instruments, Dolby and nearly all the industry bigwigs in the computer, consumer, and semiconductor industry segments. Altogether, the HDMI Forum now includes over 80 companies.

I would expect the new HDMI 2.0 standard to include the considerations of all the customers that these companies serve. As a result, verifying HDMI 2.0 compatibility across a broad range of devices is likely to be very challenging, and waiting for plug fests to find compatibility issues will sink time-to-market.  For that reason, Cadence is delivering HDMI 2.0 verification IP (VIP) to enable pre-silicon verification of SoC interfaces.  This VIP will speed the development of critical SoCs underlying Ultra HD TVs and make this new consumer entertainment experience a global reality.

For more information:

http://www.cadence.com/ip/verification_ip/Pages/hdmi.aspx

http://www.techhive.com/article/2024911/oled-and-4k-at-ces-2013-the-fantasy-and-the-reality-video-.html

http://hometheaterreview.com/is-hdmi-20-coming-soon-to-a-home-theater-near-you/

The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer number of attendees and the broad spectrum of the technology industry they represented.

Intel's embrace of a more diversified computing ecosystem was on display -- Android mascots, tablets, and phones, and yes, servers and cloud software. Intel led the PC revolution with its x86 family of processors, but faces intense competition in the handheld space where low power competitors hold sway. The keynote speeches and technical sessions were rich in content. Topics ranged from the Quark family of SoCs to Moore's Law and Big Data, and everything in between.

On Day 1, new Intel CEO Brian Krzanich talked about the evolution from a CPU based architecture to an SoC based architecture. Renee James, Intel President, discussed integrated computing and the impact on daily tasks and our lifestyle. The second day covered topics on Mobility, a key area of focus for Intel as it attempts to gain share in the handheld, mobile, and wearable computing market.

While the days were packed with technical talks on all kinds of topics from HTML5 and Hadoop to overclocking for high performance gaming and content creation, the technology showcase was a reflection of the technology ecosystem. The show floor was grouped into regions (NVM Express, Superspeed USB, etc). 

Cadence booth at IDF13 manned by Rajkumar Chandrashekhar, Engineering Director 

Sponsors and exhibitors showcased everything from malware detection (Intel's McAfee) to instrumentation (LeCroy). Team Cadence was present in full force, with booth coverage from Bangalore, Austin, and San Jose! The piece de resistance at out booth was an interoperability demo of Cadence's MPCIe controller and MPHY, interoperating with Intel's MPCIe controller. The Intel and Cadence team had collaborated over the summer to make this happen. (This was the next step forward from our last demo at MIPI Allliance meeting and PCI SIG Devcon in June). Intel's Mahesh Wagh, lead author of the M-PCIe specification, conducted a technical session on the topic in the High Speed Peripherals track. His presentation can be found here SF13_HSTS003_100.pdf.

The event was an opportunity for Cadence and Intel to show a working demonstration of the new standard to ecosystem partners and customers. Visitors were impressed with the working combination of controller and M-PHY. Cadence's M-PHY has been used in many deployments in SoCs and application boards using the M-PHY have been used across the industry to verify a wide range of MIPI controllers. Interestingly, at the event, Cadence's M-PHY was spotted at an SSIC demo in an unrelated booth!

IDF continues to be a testament to the diversity of the technology industry and how Intel and other companies are collaborating with each other, where roles are at times fungible, changing from partner to customer to competitor. We can't wait to see some of the announcements from IDF13 become reality! 

Arif Khan 

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I attended two consecutive automotive Ethernet events near Stuttgart last week. Judging by the level of participation automotive Ethernet is really taking off. 

The first event was the OPEN Alliance face-to-face meeting which 150 people attended. The main purpose of the OPEN Alliance is to promote standards for the operation of 100M and 1G Ethernet PHYs over a single twisted pair (STP) of copper cable in automotive environments. Broadcom has brought a 100M Ethernet automotive PHY to market and NXP is going to be a second source for this. For 1G there is now the IEEE 802.3bp task force developing a standard for an automotive STP PHY. The OPEN Alliance did much of the groundwork that enabled this project to get initiated. Single twisted pair cabling has cost and weight advantages over other forms of cabling.

The second event followed on immediately after the OPEN Alliance meeting and was focused on Automotive Ethernet technology and was not limited to members of the OPEN Alliance. 450 people came to this event to listen to presentations, network with industry executives, and demonstrate their own technology in the exhibition hall. BMW, a prominent member of the Ethernet Alliance, showed off their new BMW X5 which is the first production car to incorporate 100M STP Ethernet. It uses Ethernet to connect four cameras to a central display unit.

The exhibition hall contained many demonstrations of Ethernet technology from different vendors working together. This is one of the main advantages of Ethernet, there is a wide ecosystem of support for it and it is a well understood technology. NXP demonstrated inter-operability between their 100M STP PHY and the Broadcom PHY. Marvel demonstrated a 100M PHY conformant to the IEEE 100BASE-TX standard running over two twisted pairs of copper cable and hardened for automotive environments. KDPOF demonstrated a 1G PHY running over MOST-type plastic optical fiber cables using Avago transceivers. Because these PHYs all use standard media independent interfaces they will work with any Ethernet controllers.

Cadence had a booth at which we talked about the good support Cadence has for automotive Ethernet in its IP offering, Palladium verification acceleration platform and Sigrity board design tools.

 Arthur Marris - October 2013 

Related stories:

--IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs

--One Oil Change and Update my Car to the Latest Software Patch, Please! 

Mobile is the only business besides PCs where actual SoCs get a lot of visibility in the eyes of the end customer. Does Joe Doe care what’s inside his MP3 player or car infotainment system? No, not as long as it’s doing its job. But when it comes to his smartphone or a tablet, his awareness of the chip inside is much higher.

It’s good for the business, because this awareness helps IP providers promote solutions that are little marvels of engineering and take time to develop. It keeps the business going, as we know the customers will ask for a next-gen solution in no more than a year.  This drives revenue growth, because nothing is worth more than a slight competitive edge that secures a big win in the market.

It’s also bad for the business, because only a few companies can keep up with the pace of this race. Also, the money involved is high, so you want to place your bets carefully. And last but not least, you’re developing technology that is silicon-proven by you and is production-proven also by you – this pressure does not help either.

Like it or not, the benefits outweigh the drawbacks, and cheers to that, as this keeps us going. What developers need to make sure of is that they are choosing their silicon path wisely and that the available IP fits their tight design schedules.

According to TSMC, their 28nm technology “delivers twice the gate density of the 40nm process and also features an SRAM cell size shrink of 50 percent”. Moreover, the 28HPM process (High Performance Mobile) “can provide better speed than 28HP and similar leakage power as 28LP.”

Qualcomm, among several other fabless companies, is already aboard this node with its latest Snapdragon processors that are hitting the consumer market right now inside Samsung’s Galaxy S4 and Sony’s Xperia Z Ultra smartphones. It is only a matter of time until other companies announce the availability of SoCs in this node.

Samsung Galaxy Note 3 - the latest device powered by the Qualcomm's Snapdragon 800 in 28HPM
(Photo credit: Samsung)

Leading IP providers are now releasing more and more 28HPM targeted IP, with Cadence offering USB, DDR, and PCIe PHY IP for this node.  The maturity of tools and the fact it’s all been silicon-proven make it a safe bet for risk-averse customers.

Given all this information, what’s in it for an SoC developer? Basically, everything. It’s accepted by the major players in the mobile space, the tools and IP is there, and there are enough benefits of the technology to make the investment and see how it comes back with orders for chips.

And like with everything, there is always a certain timeframe for when it’s good to do something. With FinFET, or even 20nm just around the corner, the perfect time for a 28nm mobile SoC is now!