Clik here to view.
Interconnect Beyond PCIe: CXL and Cache Coherent Interconnect
As the de facto IO interconnect technology, PCIe has commendably addressed the performance bottleneck at the IO interface by doubling the bandwidth support every 3-4 years over the course of 5...
View ArticleClik here to view.
Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications
Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband (NB) IoT. Three of Cadence’s customers had Tensilica Fusion F1 DSP demos on the show floor.Xinyi Information...
View ArticleClik here to view.
NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices
Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature...
View ArticleClik here to view.
Designing for the Future - Managing the Impact of Moore's Law
With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage...
View ArticleClik here to view.
SemiEngineering Article: Why IP Quality Is So Difficult to Determine
Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system...
View ArticleClik here to view.
AMBA Adaptive Traffic Profiles: Addressing The Challenge
Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and...
View ArticleClik here to view.
Is the Role of Test Chips Changing at Advanced Foundry Nodes?
Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring...
View ArticleClik here to view.
Why Software-Based GPS Is Great for Location-Based IoT Applications
At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s...
View ArticleClik here to view.
Chip Dis-integration
I was asked the following question recently.No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending...
View ArticleClik here to view.
Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for...
View ArticleClik here to view.
First Look: Cadence Subsystem SoC for PCIe 5.0
If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest technology in...
View ArticleClik here to view.
See You in Barcelona at MWC!
I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence...
View ArticleClik here to view.
Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP
What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers...
View ArticleClik here to view.
Why Software-Based GPS Is Great for Location-Based IoT Applications
At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s...
View ArticleClik here to view.
Chip Dis-integration
I was asked the following question recently.No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending...
View ArticleClik here to view.
Introducing Cadence IP for PCIe 6.0
Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous in the modern digital world. Today, PCIe is an indispensable technology found in high-performance computing,...
View ArticleClik here to view.
PIPE SerDes Architecture for PCIe Gen 5 and Beyond
Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification has been ubiquitous PHY interface for accelerating the design and verification of higher layer protocol stacks for...
View ArticleClik here to view.
See You in Barcelona at MWC!
I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence...
View ArticleClik here to view.
PCIe for Automotive - DesignCon/DriveWorld 2021
DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint event this year. Cadence had an opportunity to present at a session on behalf of PCI-SIG. The topic of the...
View ArticleClik here to view.
Improving Performance and Throughput While Implementing FFT Using Tensilica...
Fast Fourier transform (FFT) is a very useful block in Automotive ADAS radar, communications, robotics, and image processing. The standard FFT architectures require data re-order (Radix-2 approach) or...
View Article