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Chip Dis-integration
I was asked the following question recently.No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending...
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Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications
Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband (NB) IoT. Three of Cadence’s customers had Tensilica Fusion F1 DSP demos on the show floor.Xinyi Information...
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Is Ethernet Ready for the Automotive Market?
Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex...
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Evolution of DisplayPort
In 2006, the Video Electronics Standards Association (VESA) designed a new display interface to compete with HDMI: the DisplayPort. Since then DisplayPort has become more and more popular in the...
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NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices
Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature...
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NVMe 2019 Developer's Conference: NVMe 1.4 Is Almost Here, and Enterprise and...
Unlike previous years, the annual NVM Express Developer’s Conference was held in Fremont instead of San Jose. A well-attended event for the 120+ member consortium, this was a fantastic opportunity for...
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Designing for the Future - Managing the Impact of Moore's Law
With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage...
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SemiEngineering Article: Why IP Quality Is So Difficult to Determine
Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system...
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AMBA Adaptive Traffic Profiles: Addressing The Challenge
Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and...
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How to Verify Performance of Complex Interconnect-Based Designs?
With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of...
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Is the Role of Test Chips Changing at Advanced Foundry Nodes?
Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring...
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Dimensions to Verifying a USB4 Design
Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can...
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PCIe 3.0 Still Shines While PCIe Keeps Evolving
PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile,...
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Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier...
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PCI-SIG DevCon 2019 APAC Tour: All around Latest Spec Updates and Solution...
PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year...
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USB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers
USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each...
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Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple
Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality.The diagram below shows...
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Why Is the Evolving HBM3 Such a Revolutionary Technology and How Can You Be...
Since 2013, we have seen the HBM specifications being released by JEDEC and companies announcing in the same month HBM products just like magic. How can these companies have a silicon-proven product...
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Sizing Up eUSB2 Verification
USB is one of the most widely used interfaces in the PC market for more than 20 years. Though it remains the same form in laptops and servers, it never stops its evolution in terms of capacity and...
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Catching up with Higher Ethernet Speed: VIP Supports 802.3ck
Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE in Dec 2019. This draft provided the standardization of higher lane speed support for backplane systems, including 3...
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